Etching method in a semiconductor processing and etching system for performing the same

ABSTRACT

Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of co-pending U.S. application Ser. No.10/426,988, filed on Apr. 30, 2003, the disclosure of which isincorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to an etching method insemiconductor processing and an etching system for performing the same,and more particularly, to an etching method in semiconductor processingfor reducing a pattern loading phenomenon occurring at regions of asemiconductor device during plasma-based dry etching.

2. Description of the Related Art

Recently, the design of devices utilizing semiconductors has progressedrapidly due to the wide spread use of information media such as personalcomputers, mobile devices, mobile phones, etc.. In turn, this rapidprogression has demanded semiconductor devices to function at highoperating speeds and to have large storage capacities. In order tosatisfy such requirements, semiconductor devices with increasedintegration, reliability, and response time are aggressively beingdeveloped. To accomplish a highly integrated device, a reduction of amemory cell size is essential and, accordingly, the reduction of thesize and margin of every pattern formed on a substrate of thesemiconductor device must also be reduced. However, as a footprint of asemiconductor device decreases, a vertical size of the device, that is,an aspect ratio of elements forming the device, increases in order tomaintain performance characteristics, for example, thicker metalinterconnections lines to satisfy electrical conductivity requirements.

The technique for forming wiring patterns among various patterns, suchas a gate pattern, a bit line, and the like, is regarded as basic forthe manufacture of a semiconductor device and is a measure of totalprocessing efficiency. In the current semiconductor device design, thecritical dimension (CD) of the patterns of the gate and the bit line isparticularly narrow and an aspect ratio of the patterns is especiallyhigh. In order to form patterns having a good profile, uniformity of thecritical dimension on a whole wafer is necessary and a process change indry etching according to the pattern density is required to be small.

Generally, a plurality of etching processes are executed using a plasmasource in order to form patterns. However, during the execution of theetching, a pattern loading phenomenon occurs, which exhibits differentetching rates at different regions due to a difference in patterndensities. That is, the etching at a cell region where the patterndensity is high is slow, while an over-etching occurs at a peripheralregion where the pattern density is low. This phenomenon becomes moreand more severe as the wafer processing progresses. The intensificationof the pattern loading phenomenon is caused by by-products generatedduring implementation of the etching. The by-products generated duringthe etching of a predetermined material adversely affect a subsequentwafer to be processed.

In particular, when executing a dry etching for forming a gate by meansof a dry etching apparatus, such as the DPS Centura system commerciallyavailable from Applied Materials of Santa Clara, Calif., which uses adecoupled plasma source in order to form a gate pattern, the etchingby-products generated at the cell region where the pattern density ishigh are not readily removed as the etching proceeds. The by-productsaffect the etching on the wafer and slow down the etching rate, so thatresidues remain on the wafer. However, at the peripheral region wherethe pattern density is low, the removal of the by-products is performedmore easily and the generated by-products can be removed in a short timeperiod to provide good etching surroundings, so that the etching isperformed to a desired degree. When considering the balance of theetching rates at the two regions of the cell region and the peripheralregion, the peripheral region is generally over-etched to attack anunderlying layer of a gate oxide layer. This phenomenon will bedescribed in more detail referring to the attached drawings.

FIGS. 1A and 1B are cross-sectional views of a semiconductor device forcomparing etching aspects due to pattern loading at various patterndensities. FIG. 1A corresponds to an etching aspect of a gate pattern ata cell region where the pattern density is high, while FIG. 1Bcorresponds to an etching aspect of a gate pattern at a peripheralregion where the pattern density is low.

Referring to FIG. 1A, a gate pattern 14 c is formed on a substrate 10 atthe cell region by etching polysilicon from the substrate using aphotoresist pattern as a mask and by using decoupled plasma. Thepolysilicon is not completely removed through the etching and a residualpolysilicon layer 12 remains on the substrate 10.

Referring to FIG. 1B, a gate pattern 14 p is also formed on thesubstrate 10 at the peripheral region by etching polysilicon using thephotoresist pattern as the mask and by using the same decoupled plasma.At the peripheral region, the polysilicon is completely etched andresidual polysilicon does not remain, unlike at the cell region. Theetching rate at the cell region where the pattern density is high isslowed down gradually when compared with the etching rate at theperipheral region where the pattern density is low during theimplementation of the etching for the same time period, leaving residuesat the cell region.

If the etching time is controlled to a point when the polysilicon at thecell region is completely removed, an over-etching might be induced atthe peripheral region resulting in damage to an underlying layer, thatis, a gate oxide layer.

In order to prevent this phenomenon, an EPD (end point detection) systemmay be used by which an etching end point can be noted by measuring aradiating amount of an inherent wavelength of the material to be etchedfrom the wafer. The determination of the etching time by using the EPDsystem is accomplished by measuring the lowering of the etching rate atthe cell region. Accordingly, the etching time is lengthened graduallyaccording to the progress of the wafer processing. Through theapplication of this system, the remaining residues at the cell regioncan be partially prevented. However, since the EPD system utilizes amean etching time to prevent the phenomenon, it is inevitable thatover-etching at the peripheral region where the pattern density is lowwill occur.

Various other methods have been proposed to improve processcharacteristics in a plasma chamber.

Korean Laid-Open Patent Publication No. 2001-4243 discloses a cleaningmethod of a plasma chamber of a semiconductor manufacturing apparatus.This method includes a first step of performing an appropriate process(e.g., an etching process) in a plasma chamber, and a second step ofplasma cleaning in order to remove deposited polymer on an inner sidewall of the plasma chamber at a bottom bias power of approximately zeroor a small value of about 1-800 W, while a running wafer remains in thechamber. According to this method, the cleaning effect onto the innerwall of the chamber is maximized, while an affect onto the wafer by theplasma can be minimized at the same time. In addition, a wet cleaningperiod of the apparatus can be remarkably increased. This method can beapplied to apparatuses other than an etching apparatus, for example, itmay be applied to a cleaning of a chamber of a depositing apparatususing plasma.

However, according to this method, the cleaning is executed by settingthe bias power to zero or to a small value in order to remove residuesafter completion of the etching process. Therefore, an etching againsteven a trace amount of a pattern will generate pattern damage. As aresult, this method is applicable to a layer having a pattern of littlestep after completing the etching process, for example, after completingan etch back process. However, this method is not applicable aftercompleting an etching to form a pattern having a step to some degree.

Korean Laid-Open Patent Publication No. 1999-71110 discloses a method ofcontrolling charged impurities of a plasma etching apparatus formanufacturing a semiconductor device. This method includes the steps ofstabilizing a chamber, etching by applying a source power and a biaspower to an upper and lower electrode, respectively, forming plasma byproviding an inert gas while applying the source power and not applyingthe bias power and exhausting a cooled gas at the same time, formingplasma by providing an inert gas while not applying the bias power, andtransferring a wafer after completion of the etching process.

According to this method, charged particles and falling particles do notadhere onto a surface portion of the wafer after completion of theetching process to improve a yield of the wafer. However, the process iscomplicated and an undesirable etching might be implemented on the waferas a side effect as in the above-described method.

Japanese Laid-Open Patent Publication No. Hei 8-111402 discloses amethod of dry etching and an apparatus for implementing the method.According to this method, a porous plate having a plurality of minutepores is installed between a plasma generating portion and a samplesupporter for supporting a processing body. A bias power is not appliedto the sample supporter. Then, ions among the plasma and activatedspecies produced by the plasma are imparted with a drifting directionwhile passing through the minute pores of the porous plate, to beintroduced onto the processing body to accomplish vertical etching.

Although various methods for the plasma dry etching have been proposedas described above, a need exists for an etching method and an etchingsystem for performing the same to reduce the effects of the patternloading phenomenon caused by the difference of the etching rates betweenpatterns having different pattern densities.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a method of etchinga semiconductor device by which a change of etching rates of a dryetching process due to a difference of a pattern density is reduced anda vertical pattern profile is improved is provided, thereby increasing ayield of the device and improving a device quality.

In another embodiment of the present invention, a novel system ofetching a semiconductor device suitable for performing theabove-described etching method is provided.

According to an embodiment of a method of the present invention, plasmais generated while setting a bias power applied to a wafer to zero andapplying a source power. Then, an etching process onto a predeterminedlayer formed on the wafer is implemented by setting the bias power to apredetermined value.

In particular, the conditions of pressure, temperature and gasatmosphere during setting the bias power to zero and applying the sourcepower are preferably set to the same conditions as in a subsequentlyimplemented etching process. In addition, the time period for applyingthe plasma while setting the bias power to zero is preferably in a rangeof from about 5 seconds to about 90 seconds.

The method according to a preferred embodiment of the present inventionis advantageously applied when different regions of a semiconductorsubstrate having different pattern densities are formed after completingthe etching process, because the pattern loading phenomenon is reduced.An etching process for forming a gate pattern can be illustrated as anexample of the etching process.

Further, the step of generating plasma while setting a bias powerapplied to a wafer to zero and applying a source power and the step ofimplementing an etching process by setting the bias power to apredetermined value are preferably executed in-situ.

According to a further embodiment of the present invention, an etchingsystem in a semiconductor processing is provided. The system includes achamber for implementing a plasma etching reaction and a first RF (radiofrequency) generator for providing a source power for generating plasmain the chamber. A first switching apparatus controls an on/off operationof the source power. A second RF generator provides a bias power into achuck installed within the chamber in order to impart a directionalcharacteristic onto the produced plasma and a second switching apparatuscontrols an on/off operation of the bias power. Also, a controllercontrols an operation of the first and second switching apparatuses.

According to various embodiments of the present invention, by-productsgenerated during a preceding etching process are readily removed duringimplementation of an etching process using a plasma source and so anetching process change due to a difference of pattern densities can bereduced. As a result, a progressive pattern loading generated as anumber of processed wafers increases can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and advantages of the present invention willbecome readily apparent by reference to the following detaileddescription when considered in conjunction with the accompanyingdrawings wherein:

FIGS. 1A and B are cross-sectional views for comparing etching aspectsof a semiconductor substrate due to a pattern loading at various patterndensities;

FIG. 2 is a schematic cross-sectional view of a decoupled plasmaapparatus for implementing a dry etching process;

FIGS. 3A to 3C are schematic diagrams illustrating movements of reactinggases according to an application of a source power and a bias powerduring the implementation of a dry etching process;

FIG. 4 is a process flow chart illustrating an etching method forimplementing a plasma etching according to an embodiment of the presentinvention; and

FIGS. 5A and 5B are cross-sectional views of a gate pattern formed byimplementing a dry etching according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, preferred embodiments of the present invention will bedescribed in detail.

FIG. 2 is a schematic cross-sectional view of a decoupled plasmaapparatus for implementing a dry etching process.

A decoupled plasma apparatus mainly includes a chamber 20 which is earthgrounded, a first generator for providing a source power 46 forgenerating a magnetic field in the chamber 20 of RF (radio frequency) toproduce plasma, a source power controller 48 for controlling anapplication or not, an intensity, an applying time, etc. of the sourcepower 46, a second generator for providing a bias power 26 forgenerating an electric field of RF to impart a directionalcharacteristic to thus produced ions of the plasma and a bias powercontroller 28 for controlling an application or not, an intensity, anapplying time, etc. of the bias power 26.

A first switch for the source power 44 is turned on to supply the sourcepower 46 to a coil 42 that wraps a dome-shaped upper portion of thechamber 20 to generate the magnetic field in the chamber 20 and toproduce plasma 36. When a second switch for the bias power 24 is turnedon to supply the bias power 26 to an electrostatic chuck (ESC) 22installed at the lower portion of the apparatus for receiving a wafer30, a biased electric field is generated by the electrostatic chuckhaving appropriate voltage and applied to produced ion in advance of theetching process. Reacting gases for an etching are introduced into thechamber 20 through a gas inlet 32 and then exhausted out through anoutlet 34. By an action of the ions and radicals drifted toward thewafer 30 according to the above-described principle, a dry etching ismainly executed at a surface portion of the wafer 30.

When the source power 46 is applied without applying the bias power 26,the plasma is generated, however, the biased electric field is notgenerated. Therefore, the plasma does not have the directionalcharacteristics to etch both the side wall portion of the apparatus andthe surface portion of the wafer at the same etching rate. Here, sincethe etching rate onto the wafer is about 5% or less when compared to anetching rate when the bias power is applied, the wafer might be scarcelyetched while the by-products adhering to the side wall portion of theapparatus can be easily removed.

The on/off operation of the first and the second switch 44, 24 can becontrolled by means of a separately provided switch controller 50. Thatis, the on/off operation of the first and second switches 44 and 24 forcontrolling the application or not of the source power 46 and the biaspower 26, respectively, can be automatically controlled by determiningan on/off time at an initial step when determining a sequence and theninputting the determined result into the switch controller 50.

FIGS. 3A to 3C are schematic diagrams illustrating movements of reactinggases according to an application of a source power and a bias powerduring implementation of a dry etching process.

Referring to FIG. 3A, CF₄ is used as a reacting gas. When the switch forthe source power is turned on for applying RF of several tens of MHzinto the coil 42, plasma is produced in the chamber and cations andanions are separated. At this time, light anions might readily andrandomly move, however, heavy cations hardly move. Accordingly, anionssuch as fluoride ions F mainly move in all directions and impact thewafer 30 and the inner wall portion of the etching chamber 20, asillustrated in FIG. 3A.

Referring to FIG. 3B, CF₄ is used as a reacting gas and both the sourcepower and the bias power are applied. When the bias power is applied tothe chuck 32 supporting the wafer 30 to generate a biased electricfield, most of active species such as ions, radicals, etc. move towardsthe wafer. That is, an etching process is executed at the surfaceportion of the wafer by the reactive ions, radicals, etc.

Referring to FIG. 3C, a schematic diagram is illustrated when Cl₂/SF₆ isused as reacting gases and both the source power and the bias power areapplied.

According to an embodiment of the present invention, a wafer isinstalled on a chuck for implementing a dry etching process onto apredetermined layer formed on the wafer and then an etching condition isset, e.g., pressure, temperature, gas atmosphere, etc.. A source poweris applied without applying a bias power during a predetermined periodof a pre-etching process, just before executing the etching process byapplying the source power and the bias power. Through the pre-etchingprocess, the etching condition is completely set during a sufficienttime period and by-products in the chamber are removed. After completionof the setting of the etching condition within the chamber and removingthe by-products to a desired degree, the etching process onto the waferis started. Accordingly, an etching characteristic is good and a patternloading phenomenon generated at regions having different patterndensities can be largely reduced.

In addition, even though a small amount of a target layer formed on thewafer is etched during the pre-etching period with the application ofthe source power, this etching is executed onto the target layer to beetched during a subsequently executed etching process. Therefore, theetching of the small amount of the target layer during the pre-etchingperiod does not matter.

FIG. 4 is a process flow chart for implementing a plasma etchingaccording to an embodiment of the present invention.

First, a wafer to be etched is loaded on a chuck in a chamber (stepS10). An etching gas is introduced, under the same conditions as insubsequently applied etching conditions, onto a target layer to beetched (step S20). A bias power is set to zero, a source power isapplied according to an instruction signal from a controller forapplying a source power and a first switch for controlling an on/offoperation of the source power is turned on (step S30). With theapplication of RF power into a wound coil around an upper dome-shapedportion of the chamber, plasma is generated in the chamber (step S40).After a given period of time, a pre-etching within the chamber iscompleted. Then, a bias power is applied and a second switch forcontrolling an on/off operation of the bias power is turned on (stepS50). When the bias power is applied into the chuck on which the waferis loaded, the plasma having a directional characteristic is used foretching the target layer (step S60).

Hereinafter, a preferred embodiment of the present invention will bedescribed in more detail.

An embodiment of the present invention will be described referring to anetching process for forming a gate pattern, e.g., a basic pattern formanufacturing a semiconductor device. The gate is generally formed frompolysilicon/WSi, and an anti-reflective layer, e.g., comprised of SiON,is formed on the gate. The etching process is executed using a hard masksuch as a SiN mask. It is to be understood these substances areillustrated for explanation purposes and the method of the presentinvention may be applied to every kind of etching process withoutexception.

First, a wafer including a polysilicon layer, a tungsten silicide (WSi)layer and an anti-reflective layer is installed on a chuck into which abias power is to be applied, within a chamber.

Next, plasma is generated by applying a source power for about 5-90seconds to an etching gas including CF₄/Ar within the chamber, whilesetting the bias power to zero. At this time, active species might reactas illustrated in FIG. 3A. When the inner portion of the chamber isstabilized, the bias power of a predetermined value is applied to etchthe anti-reflective layer. Through the application of the bias power,active species obtain a drifting direction and move toward the wafer toaccomplish the etching as illustrated in FIG. 3B.

The time required for the pre-etching is not specifically limited. Afterrepeating a number of experiments, the inventors of the presentinvention have found that the preferred and sufficient pre-etching timeis in a range of about 5-90 seconds when considering an effect of theresulting reduction of the pattern loading. However, the pre-etchingtime may be increased or decreased. More preferably, the pre-etchingtime is in a range of about 15-60 seconds.

When generating the plasma by applying only the source power withoutapplying the bias power under the same conditions as in the subsequentlyimplemented etching process, various ions and radicals of the plasmarandomly collide onto the wall of the chamber to remove residualby-products in the chamber. The pattern loading phenomenon is generatedfrom the initial step of the etching and becomes gradually severe withthe lapse of time and with the increase in the number of the wafersprocessed. However, when the pre-etching process is implemented beforeetching each wafer, the residual by-products can be readily removed.Conventionally, the cleaning of the inner portion of the chamber using acleaning gas has been performed for a constant time period, for example,once a day or once per several hour period. When compared to theconventional method, the method of the present invention is very simpleand efficient. In addition, the conventionally used cleaning gas, suchas SF₆, is not separately used and special conditions are not requiredto be set according to the present invention. Further, since thecondition for the pre-etching process applied in the present inventionis the same as in the subsequently executed etching process, time andeffort can be largely saved.

After completing the etching of the anti-reflective layer, an etchingonto the WSi layer is executed. To execute this etching process, aprocessing gas, such as Cl₂/SF₆, is introduced. At this stage, sinceactive species produced from the processing gas, such as Cl₂/SF₆ , havethe directional characteristic as illustrated in FIG. 3C, an etchingonto the WSi layer is accomplished. Before executing this etchingprocess, a pre-etching process can be carried out under the same etchingcondition except that a source power is applied and a bias power is setto zero.

When an etching condition is changed, a novel etching condition is set.During the pre-etching process, the newly applied etching conditioncould be controlled to completely set the etching condition by applyingonly the source power to remove the by-products in the chamber. Some ofthe pre-etching processes perform in accordance with a plurality ofetching processes could be omitted as occasion needs.

After etching the WSi layer to a satisfactory degree, the polysiliconlayer is etched. At the time when the etching of the WSi layer iscompleted, a processing gas of HBr/O₂ is introduced to complete theetching of the polysilicon layer.

The etching onto the WSi layer and the polysilicon layer is stopped whenan underlying gate oxide layer is exposed. The etching of thepolysilicon is mainly achieved by an action of the HBr/O₂ gas plasma.Through using this condition, by-products strongly adhere to the surfaceportion of the oxide to passivate the gate oxide layer.

A mechanism for etching the polysilicon is illustrated as in reactionequation (1).HBr+O₂+polysilicon (poly-si)→SiBr_(x)(↑)+SiO₂+H₂O+OH+H₂O₂  (1)

When the gate oxide layer is exposed, the surface passivating reactionis attained as the following reaction equation (2).HBr+O₂+SiO₂→BrO₂ (passivation)+Br₂O (passivation)+H₂O  (2)

When the gate oxide layer is exposed, by-products generated during theetching such as oxide compounds along with silicon oxide adhere onto thesurface portion of the oxide layer and the side wall of the apparatus topassivate the gate oxide layer. These oxide compounds oxidize thesurface portion of the WSi layer during etching for the passivation, theWSi layer being formed on the subsequently processed wafer. Inparticular, the amount of the passivating oxide compound is large at thecell region where the pattern density is high when compared to theperipheral region where the pattern density is low, and therefore, thepattern loading phenomenon at the cell region appears even more severe.Accordingly, as the number of the wafers increases during a process run,the amount of the oxides for passivating the surface portion of the WSilayer increases and the etching rate at the cell region is graduallylowered to generate a progressive pattern loading phenomenon. When theoxides, which are factors of the passivation, adhere onto the side wallof the apparatus and are removed before the etching of the WSi layer,the progressive pattern loading at the cell region and the peripheralregion will be reduced.

In conclusion, when a new wafer is installed for executing an etching, apre-etching is implemented under the same condition as a subsequentlyexecuted etching process except that the bias power applied to the chuckis turned off and the source power is turned on, to stabilize thesubsequently executed etching condition and to remove by-productsadhered onto the side wall of the apparatus.

FIGS. 5A and 5B are cross-sectional views of a gate pattern formed byimplementing a dry etching according to an embodiment of the presentinvention. FIG. 5A corresponds to gate patterns formed at a cell regionwhere the pattern density is high, while FIG. 5B corresponds to a gatepattern formed at a peripheral region where the pattern density is low.

When comparing the gate pattern 114 c formed at the cell region and thegate pattern 114 p formed at the peripheral region on the substrate 110,the gate pattern 114 p at the peripheral region is formed to have acompletely etched shape, and the gate pattern 114 c at the cell regionis formed to have a satisfactory degree of etching even though someresidues of polysilicon 112 remain. In particular, when compared to thegate patterns formed by the conventional etching method as illustratedin FIGS. 1A and 1B, the pattern loading phenomenon at the cell regionwhere the pattern density is high is largely reduced and the amount ofthe remaining residues is remarkable decreased.

According to another embodiment of the present invention, a pre-etchingis applied using a target wafer to be etched for the formation of apattern for stabilizing a chamber of a dry etching apparatus beforeetching the wafer for patterning and for reducing a pattern loadingphenomenon. In addition, a time consumed for the pre-etching is largelyreduced when compared with that for cleaning using a dummy wafer.According to the conventional method of using the dummy wafer, severalminutes of time is required to transfer the wafer and for loading theapparatus while about 10-30 seconds are required for implementing a dryetching process. Accordingly, when a pre-etching is executed using thetarget wafer and then dry etching is executed in-situ according to themethod of the present invention, the time required for the transfer ofthe wafer and the loading of the apparatus can be saved to largelyreduce a processing time.

Here, the differences between the various embodiments of the presentinvention and the method disclosed in Korean Laid-Open PatentPublication No. 2001-4243 will be described.

According to the conventional method described in the above publication,a plasma cleaning method for removing a polymer deposited on an innerwall of a plasma chamber, is executed after completing an etchingprocess within the plasma chamber before unloading a wafer from a chuckin the chamber. A bottom bias power is set to zero or a to a small valueof about 1-800 W. According to this method, a good cleaning effect ontothe inner wall of the chamber is obtainable.

However, since the cleaning is executed after completing the etchingprocess, while setting the bias power to zero or the small value toremove by-products, a pattern damage is generated even though a smallamount of etching onto the formed pattern is allowable. Therefore, thismethod is applicable to a layer including little steps such as a layerobtained after implementing an etch back process. However, this methodis not applicable after executing an etching for forming a patternhaving a large step. In conclusion, the above method is applicable to aprocess for reducing topology during manufacturing a semiconductordevice.

In contrast, according to an embodiment of the present invention, plasmais provided into a chamber before etching under the same condition ofthe etching process. So, an effect of setting an etching conditionbefore implementing the etching and of removing by-products within thechamber to reduce the pattern loading phenomenon at the region where thepattern density is high after completing the etching process, can beaccomplished. Therefore, no damage is generated onto a target layer tobe etched and an even better effect may be obtained when forming apattern having a high topology according to the present invention.

The etching method according to embodiments of the present inventionalso can be automatically applied through determining an applying timeof a bias power and a source power and then fixing the determined resultin a controller by an operator of the apparatus.

As described above, by-products generated during successive etchingprocesses can be readily removed during implementation of a pre-etchingprocess using a plasma source and a change in etching rates due to adifference of pattern densities realized during etching can be reducedaccording to an embodiment of the present invention. Therefore, apattern loading phenomenon, which increases as a number of processedwafers increases, can be prevented. As a result, a vertical profile of apattern is improved and production productivity of devices is increased.

In addition, since plasma is provided under the same condition as in anetching during a pre-etching process, a cleaning effect of an apparatusis obtainable through an in-situ operation. Accordingly, productivity ofthe apparatus is increased and maintenance costs of the apparatus can bereduced.

Further, a pre-etching is executed using a target wafer to be etched inaccordance with an embodiment of the present invention and so a timerequired for cleaning is largely reduced when compared with a methodusing a dummy wafer. According to the conventional method of using thedummy wafer, several minutes of time is required for transferring awafer and for loading an apparatus and about 10-30 seconds of time isconsumed for executing a practical dry etching. When a pre-etching isexecuted while installing a target wafer and then an etching for formingline and space of a pattern is executed in-situ according to anembodiment of the present invention, the time required for transferringthe wafer and for loading the apparatus can be saved, thereby largelyreducing a processing time.

Although the preferred embodiments of the present invention have beendescribed, it is to be understood that the present invention should notbe limited to these preferred embodiments but various changes andmodifications can be made by one skilled in the art within the spiritand scope of the present invention as hereinafter claimed.

1. A system for etching a semiconductor device, comprising: a chamberfor implementing a plasma etching reaction; a first RF (radio frequency)generator for providing a source power for generating plasma in thechamber; a first switching apparatus for controlling an on/off operationof the source power; a second RF generator for providing a bias power toa chuck installed within the chamber to impart a directionalcharacteristic onto the generated plasma; and a second switchingapparatus for controlling an on/off operation of the bias power.
 2. Asystem for etching a semiconductor device as claimed in claim 1, furthercomprising a controller for controlling an operation of the first andsecond switching apparatus.
 3. A system for etching a semiconductordevice as claimed in claim 1, wherein a wafer on which patterns havingdifferent pattern densities are formed by a subsequent etching process,is provided on the chuck.
 4. A system for etching a semiconductor deviceas claimed in claim 1, wherein the first RF generator generates amagnetic field onto a processing gas to generate the plasma.
 5. A systemfor etching a semiconductor device as claimed in claim 4, wherein theprocessing gas is CF₄/Ar, Cl₂/SF₆ or HBr/O₂.
 6. A system for etching asemiconductor device as claimed in claim 1, wherein the second RFgenerator generates an electric field to impart the directionalcharacteristic onto the generated plasma.
 7. A system for etching asemiconductor device as claimed in claim 1, further comprising a sourcepower controller for controlling an application, an intensity and anapplying time of the source power.
 8. A system for etching asemiconductor device as claimed in claim 1, further comprising a biaspower controller for controlling an application, an intensity and anapplying time of the bias power.